1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits. More particular, the present invention relates to a CMOS (Complementary metal-oxide-semiconductor) inverter with low-power consumption.
2. Description of the Related Art
As a result of fabrication techniques which allow the miniaturization of semiconductor ICs (Integrated Circuit), many portable electronic products, such as, cellular phones, pagers, lap-top computers, notebook computers, or even sub-notebook computers, can be commercially implemented. Nevertheless, these products are powered by batteries, for instance, nickel-cadmium, nickel-hydrogen o cells. To decrease the power consumption thereof, there is a need to lower the voltage supplied to semiconductor devices.
Referring to FIG. 1, a conventional CMOS inverter is schematically depicted, which is disclosed by Assaderaghi et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation," IEEE International Electron Devices Meeting, Technical Digest, pp. 809-812, 1994; Andoh et al., "Design Methodology for Low-Voltage MOSFETs," IEEE International Electron Devices Meeting, Technical Digest, pp. 79-84, 1994; as well as Assaderaghi et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation," IEEE Electron Device Letters, Vol. 15, pp. 510-512, 1994. In the drawing, the conventional CMOS inverter comprises a PMOS transistor M.sub.3 and an NMOS transistor M.sub.4. Each transistor is a four-terminal device, having a drain, a source, a gate, and a bulk, respectively. The gates of the PMOS transistor M.sub.3 and NMOS transistor M.sub.4 are connected together to form an input terminal Vin. The drains of the PMOS transistor M.sub.3 and NMOS transistor M.sub.4 are connected together to form an output terminal Vout. The source of the PMOS transistor M.sub.3 is connected to a voltage source V.sub.DD ; the source of the NMOS transistor M.sub.4 is connected to the ground. Note that both bulks of the PMOS transistor M.sub.3 and NMOS transistor M.sub.4 are connected to the input terminal Vin.
In FIG. 2 depicts the circuit diagram of a first inverter 11 and a second inverter 12 connected in series. The first inverter 11 has an input terminal Vin1 and an output terminal Vout1. Also, the second inverter 12 has an input terminal Vin2 and an output terminal Vout2. Those inverters 11 and 12 are connected in series, that is, the output terminal Vout1 of the first inverter 11 is connected to the input terminal Vin2 of the second inverter 12. According to the conventional CMOS inverter depicted in FIG. 1, the first inverter 11 constitutes a PMOS transistor M.sub.31 and an NMOS transistor M.sub.41, while the second inverter 12 consists of a PMOS transistor M.sub.32 and an NMOS transistor M.sub.42.
As shown in FIG. 2, while a logic "high" level (V.sub.DD) appears at the input terminal Vin1 of the first inverter 11, the output terminal Vout1 of the first inverter 11 reveals a logic "low" level (.apprxeq.0 V). Therefore, a body current I.sub.1, flowing through the forward-biased source-to-substrate junction of the PMOS transistor M.sub.32 in the second inverter 12, predominantly contributes a non-zero input current flowing from the source to the drain of the NMOS transistor M.sub.41 in the first inverter 11. This input current ranges from about 10.sup.-11 A to 10.sup.-7 A for the voltage source V.sub.DD from 0.3 V to 0.7 V. Although the inverter is operated at a steady state (Vin1=V.sub.DD), this non-zero input current I.sub.1 might result in a great amount of power consumption if a voltage source V.sub.DD of about 0.7 V is applied. On the other hand, another body current, flowing through the forward-biased bulk-to-source junction of the NMOS transistor M.sub.41, also contributing the non-zero input current discharges the logic level stored at the input terminal Vin1, leading to a significant increase of refresh frequency. Conversely, if a voltage source less than about 0.3 V is applied, the non-zero input current seems so small as to be negligible. However, the input impedance of the inverters 11 and 12 becomes virtually capacitive and therefore constrains the operation speed thereof.